In the design of integrated-circuit devices, decreasing the resistance-capacitance (RC) delay time in interconnect elements between the circuit elements, such as transistors, is an important goal for increasing the speed of signal transmission between circuit elements. In order to reduce the RC delay time, a known strategy is to use a porous ultra-low-k (P-ULk) insulator material to decrease the capacitance, and to use copper-containing material for the interconnect elements for providing a low resistance.
The use of copper (Cu) for conductive interconnect elements of advanced integrated-circuit devices has improved device performance due to the lower resistivity of Cu in comparison with aluminum (Al)-based conductive elements, which were previously used for this purpose. Cu-containing conductive interconnect elements also exhibit an improved electromigration performance. On the other hand, the diffusion of Cu from the conductive interconnect elements into neighboring layers is known to lead to a degradation not only of the interconnect elements, but also of the overall performance of active devices.
A prevention of Cu diffusion from the Cu-containing conductive elements, which is also referred to as passivation of the Cu-containing conductive elements in the present application, is possible by depositing a diffusion barrier and has been used extensively. For instance, U.S. Pat. No. 6,958,296 B2 describes a method for forming a titanium silicon nitride (TiSiN) diffusion-barrier layer. The TiSiN layer is deposited in a feature of the semiconductor device prior to Cu deposition, and a Cu layer is deposited over the TiSiN barrier to form the Cu-containing conductive element.
Above Cu-containing conductive interconnect elements, a dielectric barrier liner is typically deposited to achieve passivation towards higher interconnect levels. The dielectric barrier liner also plays an important role in integration schemes. It is for instance used as an etch stop layer on top of dielectric layers adjacent to the conductive interconnect element when controlling via etching to prevent an over-etching of an underlying dielectric level in an interconnect stack of an integrated-circuit device. A material frequently used is for instance SiCN.
A disadvantage of this processing is that the materials used for dielectric liners have a rather high value of the relative dielectric constant εr, which is also referred to in short as k or as the relative permittivity, especially in the context of integrated-circuit devices for high-frequency application, e.g., radio applications.
Integrated-circuit devices fabricated according to advanced processing technologies have interconnect stacks that use ultra-low-k (ULK) materials such as SiOCH (k=2.5). ULK materials improve the performance of the interconnect stack by reducing capacitance and thus, in combination with low-resistivity Cu interconnects, providing a particularly low RC product (R: resistance, C: capacitance). A low RC product reduces the delay in signal propagation along the conductive elements of the interconnect stack.
However, the use of dielectric barrier liners with higher k-values compared to the ULK material degrades the global performance of the interconnect stack since the k-value of the dielectric barrier liners strongly affect the effective dielectric constant of the interconnect stack.